During normal operation, the MPU fetches an instruction from memory and then executes the requested function. This sequence begins after RESET and is repeated indefinitely unless altered by a special instruction or hardware occurrence. Software instructions that alter normal MPU operation are: SWI, SWI2, SWI3, CWAI, RTI, and SYNC. An interrupt or !HALT input can also alter the normal execution of instructions Figure 14 is the flowchart for the MC6809E.
FIGURE 10 - CLOCK GENERATOR
NOTE: If optional circuit is not included the CLR and PRE inputs of U2 and U3 must be tied high.
FIGURE 11 - READ-MODIFY-WRITE INSTRUCTION EXAMPLE (ASL EXTENDED INDIRECT)
The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The MC6809E has the most complete set of addressing modes available on any microcomputer. For example, the MC6809E has 59 basic instructions; however, it recognizes 1464 different variations of instructinns and addressing modes. The addressing modes support modern programming techniques. The following addressing modes are available on the MC6809E:
Inherent (Includes Accumulator)
Auto Increment Decrement
Short Long Relative Branching
Program Counter Relative Addressing
In this addressing mode, the opcode of the instruction contains all the address information necessary. Examples of inherent addressing are: ABX, DAA, SWI, ASRA, and CLRB.
In immediate addressing, the effective address of the data is the location immediatelv following the opcode (i.e., the data to be used in the instruction immediately following the opcode at the instruction). The MC6809E uses both 8- and 16-bit immediate values depending on the size of argument specified by the opcode. Examples of instructions with immediate addressing are:
LDA #$20 LDX #$F000 LDY #CAT
# signifies immediate addressing;
$ signifies hexadecimal value to the MC6809 assembler.
In extended addressing, the contents of the two bytes immediately following the opcode fully specify the 16-bit effective address used by the instruction. Note that the address generated by an extended instruction defines an absolute address and is not position independent. Examples of extended addressing include:
LDA CAT STX MOUSE LDD $2000
As a special case of indexed addressing (discussed below), one level of indirection may be added to extended addressing. In extended indirect, the two bytes following the postbyte of an indexed instruction contain the address of the data.
LDA [CAT] LDX [$FFFE] STU [DOG]
Direct addressing is similar to extended addressing except that only one byte of address tollows the opcode. This byte specifies the lower eight bits of the address to be used. The upper eight bits of the address are supplied by the dira.t page register. Since only one byte of address is required in direct addressing, this mode requires less memory and exe-cutes taster than extended addressing. Of course. only 256 locations (one page) can be accessed without redefining the contents of the DP register. Since the DP register is set to $00 on reset, direct addressing on the MC6809E is upward compatible with direct addressing on the M6800. Indirection is not allowed in direct addressing. Some examples of direct addressing are:
LDA where DP = $00 LDB where DP $10 LDD <CAT
< is an assembler directive which forces direct addressing.
Some opcodes are followed by a byte that defines a register or set of registers to be used by the instruction. This is called a postbyte. Some examples of register addressing are:
TFR X, Y Transfers X into Y EXG A, B Exchanges A with B PSHS A, B, X, Y Push Y, X, 8 and A onto S stack PULU X, Y, D Pull D, X, and Y from U stack
In all indexed addressing, one of the pointer registers (X, Y, U, S, and sometimes PC) is used in a calculation at the effective address of the operand to be used by the instruction. Five basic types of indexing are available and are discussed below. The postbyte of an indexed instruction specifies the basic type and variation of the addressing mode, as well as the pointer register to be used. Figure 15 lists the legal formats for the postbyte. Table 2 gives the assembler form and the number of cycles and bytes added to the basic values for indexed addressing for each variation.
FIGURE. 15 - INDEXED ADDRESSING POSTBYTE REGISTER BIT ASSIGNMENTS
7 6 5 4 3 2 1 0 0 R R d d d d d EA = ,R + 5-bit offset 1 R R 0 0 0 0 0 , R++ 1 R R i 0 0 0 1 , -R 1 R R 0 0 0 1 1 , --R 1 R R i 0 1 0 0 EA = ,R + 0 offset 1 R R i 0 1 0 1 EA = ,R + ACCB offset 1 R R i 0 1 1 0 EA = ,R + ACCA offset 1 R R i 1 0 0 0 EA = ,R + 8-bit offset 1 R R i 1 0 0 1 EA = ,R + 16-bit offset 1 R R i 1 0 1 1 EA = ,R + D offset 1 x x i 1 1 0 0 EA = ,PC + 8-bit offset 1 x x i 1 1 0 1 EA = ,PC + 16-bit offset 1 R R i 1 1 1 1 EA = (, Address) |
| | V Addressing mode field V V i Indirect field (or sign bit when bit 7 = 0) 0 Direct 1 Indirect RR Register field 0 0 = X 0 1 = Y 1 0 = U 1 1 = S
x = Don't Care d = offset bit i = 0 = Not Indirect 1 = Indirect
In this mode, the selected pointer register contains the effective address of the data to be used by the instruction. This is the fastest indexing mode. Examples are:
LDD 0,X LDA ,S
In this mode, a two's-complement offset and the contents of one of the pointer registers are added to form the effective address of the operand. The pointer register's initial content is unchanged by the addition.
Three sizes of offset are available:
5-bit (-16 to +15)
8-bit (-128 to +128)
16-bit (-32768 to +32767)
The two's complement 5-bit offset is included in the postbyte and, therefore, is most efficient in use of bytes and cycles. The two's complement 8-bit offset is contained in a single byte following the postbyte. The two's complement 16-bit offset is in the two bytes following the postbyte. In most cases the programmer need not be concerned with the size of this offset since the assembler will select the optimal size automatically. Examples of constant-offset indexing are:
LDA 23,X LDX - 2,S LDY 300,X LDU CAT,Y
|Constant Offset From R
(2's Complement Offsets)
|5-Bit Offset||n,R||0RRnnnnn||1||0||defaults to 8-bit|
|Accumulator Offset From R
(2's Complement Offsets)
|A Register Offset||A,R||1RR00110||1||0||[A,R]||1RR10110||4||0|
|B Register Offset||B,R||1RR00101||1||0||[B,R]||1RR10101||4||0|
|D Register Offset||D,R||1RR01011||4||0||[D,R]||1RR11011||7||0|
|Auto Increment/Decrement R||Increment By 1||,R+||1RR00000||2||0||not allowed|
|Increment By 2||,R++||1RR00001||3||0||[,R++]||1RR10001||6||0|
|Decrement By 1||,-R||1RR00010||2||0||not allowed|
|Decrement By 2||,--R||1RR00011||3||0||[,--R]||1RR10011||6||0|
|Constant Offset From PC
(2's Complement Offsets)
|Extended Indirect||16-Bit Address||-||-||-||-||[n]||1xx11111||5||2|
R = X,Y,U or S x = Don't Care RR: 00 = X, 01 = Y, 10 = U, 11 = S
+ ~ and +# indicate the number of additional cycles and bytes respectively for the particular indexing variation.
This mode is similar to constant offset indexed except that the two's complement value in one of the accumulators (A, B, or D) and the contents of one of the pointer registers are added to form the effective address of the operand. The contents of both the accumulator and the pointer register are unchanged by the addition. The postbyte specifies which accumulator to use as an offset and no additional bytes are required. The advantage of an accumulator offset is that the value of the offset can be calculated by a program at run-time.
Some examples are:
LDA B,Y LDX D,Y LEAX B,X
In the auto increment addressing mode, the pointer register contains the address of the operand. Then, after the pointer register is used, it is incremented by one or two. This addressing mode is useful in stepping through tables, moving data, or creating software stacks. In auto-decrement, the pointer register is decremented prior to use as the address of the data. The use of auto-decrement is similar to that of auto-increment, but the tables. etc., are scanned from the high to low addresses. The size of the increment/decrement can be either one or two to allow for tables of either 8- or 16-bit data to be accessed and is selectable by the programmer. The pre-decrement, post-increment nature of these modes allows them to be used to create additional software stacks that behave identically to the U and S stacks.
Some examples of the auto increment/decrement addressing modes are:
LDA ,X+ STD ,Y++ LDB ,-Y LDX ,--S
Care should be taken in performing operations on 16-bit pointer registers (X, Y, U, S) where the same register is used to calculate the effective address.
Consider the following instruction:
STX 0,X++ (X initialized to 0)
Tha desired result is to store a zero in locations $0000 and $0001, then increment X to point to $0002. In reality, the following occurs:
0 --> temp calculate the EA; temp is a holding register X+2 --> X perform auto increment X --> (temp) do store operation
All of the indexing modes, with the exception of auto increment/decrement by one or a 16-bit offset, may have an additional level of indirection specitied. In indirect addressing, the effective address is contained at the location specified by the contents of the index register plus any offset. In the example below, the A accumulator is loaded indirectly using an effective address calculated from the index register and an offset.
Before ExecutionA = XX (don't care) X = $F000$0100 LDA [$10,X) EA is now $F010$F010 $F1 $F150 is now the new EA $F011 $50$F150 $AA
After ExecutionA = $AA (actual data loaded) X = $F000
All modes of indexed indirect are included except those which are meaningless (e.g, auto increment/decrement by 1 indirect). Some examples of indexed indirect are
LDA [,X] LDD [10, S] LDA [B,Y] LDD [,X++]
The byte(s) following the branch opcode is (are) treated as a signed offset which may be added to the program counter. If the branch condition is true, then the calculated address (PC + signed offset) is loaded into the program counter. Program execution continues at the new location as indicated by the PC; short (one byte offset) and long (two bytes offset) relative addressing modes are available. All of memory can be reached in long relative addressing as an effective address interpreted modulo 216. Some examples of relative addressing are:
BEQ CAT (short) BGT DOG (short) CAT LBEQ RAT (long) DOG LBGT RABBIT (long) . . . RAT NOP RABBIT NOP
The PC can be used as the pointer register with 8- or 16-bit signed offsets. As in relative addressing, the offset is added to the current PC to create the effective address. The effective address is then used as the address of the operand or data. Program counter relative addressing is used for writing position independent programs. Tables related to a particular routine will maintain the same relationship after the routine is moved, if referenced relative to the program counter. Examples are:
LDA CAT, PCR LEAX TABLE, PCR
Since program counter relative is a type of indexing, an additional level of indirection is available.
LDA [CAT,PCR] LDU [DOG,PCR]